Path: senator-bedfellow.mit.edu!bloom-beacon.mit.edu!hookup!solaris.cc.vt.edu!homer.alpha.net!uwm.edu!math.ohio-state.edu!howland.reston.ans.net!EU.net!sun4nl!wirehub!newsgate.cistron.nl!news.ow.nl!patriot.nl!zoetermeer!rijnhaave.nl!news.unisource.nl!surfnet.nl!tudelft.nl!elektron.et.tudelft.nl!einstein.et.tudelft.nl!offerman From: offerman@einstein.et.tudelft.nl (Aad Offerman) Newsgroups: comp.sys.ibm.pc.hardware.chips,comp.sys.ibm.pc.hardware.systems,comp.sys.ibm.pc.hardware.misc,comp.ibm.pc.hardware,comp.sys.ibm.pc.misc,comp.sys.intel,comp.answers,news.answers Subject: Personal Computer CHIPLIST 9.3 part 4 of 5 Supersedes: <4lluqm$j4k@elektron.et.tudelft.nl> Followup-To: poster Date: 5 Jul 1996 18:06:35 GMT Organization: Delft University of Technology, Dept. of Electrical Engineering Lines: 807 Approved: news-answers-request@MIT.EDU Expires: 28 September 1996 00:00:00 MET Message-ID: <4rjljb$mik@elektron.et.tudelft.nl> References: <4rjg4i$gjt@elektron.et.tudelft.nl> Reply-To: offerman@einstein.et.tudelft.nl NNTP-Posting-Host: einstein.et.tudelft.nl Summary: This list contains the various CPUs and NPXs and their features, used in the IBM PC, IBM PC/XT, IBM PC/AT, IBM PS/2 and compatibles, and the differences between them. Keywords: PC, CPU, NPX X-Newsreader: NN version 6.5.0 #2 (NOV) Xref: senator-bedfellow.mit.edu comp.sys.ibm.pc.hardware.chips:92106 comp.sys.ibm.pc.hardware.systems:40795 comp.sys.ibm.pc.hardware.misc:67052 comp.sys.ibm.pc.misc:85413 comp.sys.intel:96912 comp.answers:19748 news.answers:76163 Archive-name: pc-hardware-faq/chiplist/part4 Last-modified: 1996/06/25 Version: 9.3 2.41 Intel Pentium CPU 2-isue 5-stage superscalar with 8-stage pipelined FPU (Floating Point Unit). Intel i80486 CPU upward instruction compatible. Multiprocessor support. Upgrading: adding more Intel Pentium CPUs. Parity checking at busses. Branch prediction (BTB: Branch Target Buffer). 8 kbyte instruction cache, 8 kbyte data cache (Harvard architecture). Both 2-way set associative, write back, no write allocate. 32 bit internal data bus (CPU - MMU (Memory Management Unit, including cache)) 64 bit external data bus (MMU (Memory Management Unit, including cache) - memory). 32 bit address bus. Package: 296 pin PGA (Pin Grid Array). In October 1994 Dr. Thomas R. Nicely, Professor of Mathematics at the Lynchburg College, Lynchburg, Virginia (nicely@acavax.lynchburg.edu), reported a bug present in the FPU of all Intel Pentium CPUs. The double precision part of the mantissa is not computed correctly when dividing in some areas of the mantissa space of the divisor. The bug is fixed in Intel Pentium CPUs produced after November 1994. 2.41.1 Intel Pentium P5 CPU 60 MHz (Intel Pentium 510\60 CPU): 5 V, March 1993, 17-13 W, iCOMP 510. 66 MHz (Intel Pentium 567\66 CPU): 5 V, 16-13 W, iCOMP 567, 64.5 SPECint92, 56.9 SPECfp92 (First 66 MHz CPUs had heat troubles and were released as 60 MHz items). Technology: 0.8 micron biCMOS. 3.2E6 transistors. Die size: 18 x 16 mm. ID: step level Ax: DH = 0x05 (family ID), DL = 0x0X (model ID, revision), step level B1: DH = 0x05 (family ID), DL = 0x13 (model ID, revision), step level C1: DH = 0x05 (family ID), DL = 0x15 (model ID, revision), step level D1: DH = 0x05 (family ID), DL = 0x17 (model ID, revision). CPUID: step level Ax: family = 0x5, model = 0, step level Bx: family = 0x5, model = 1. Model 1, revision 7: FDIV bug fixed. 60 MHz: 80500. 60, 66 MHz: 80501. 2.41.2 Intel Pentium P54C CPU Upgrading: Intel Pentium P54M Overdrive (2 CPUs co-operating), Intel Pentium P55CT CPU. 50/75 MHz (Intel Pentium 610\75 CPU) (notebooks, P54T): 3 V, August 1994, package: 320 pin TCP, iCOMP 610. 60/90 MHz (Intel Pentium 735\90 CPU): 3.3 V, March 1994, iCOMP 735. 66/100 MHz (Intel Pentium 815\100 CPU): 3.3 V, March 1994, iCOMP 815. 60/120 MHz (Intel Pentium 1000\120 CPU): no multi-processor features, March 1995, step level C2. 66/133 MHz (Intel Pentium 1110\133 CPU): 0.35 micron CMOS. Technology: 4 layer metal, 0.6 micron biCMOS. 3.3E6 transistors. Die size: 12 x 13 mm. ID: step level A: DH = 0x05 (family ID), DL = 0x2X (model ID, revision), step level B1: DH = 0x05 (family ID), DL = 0x21 (model ID, revision), step level B3: DH = 0x05 (family ID), DL = 0x22 (model ID, revision), step level B5: DH = 0x05 (family ID), DL = 0x24 (model ID, revision), step level C1: DH = 0x05 (family ID), DL = 0x25 (model ID, revision), step level C2 (120 MHz): DH = 0x05 (family ID), DL = 0x25 (model ID, revision), P54CQS, 120 MHz: DH = 0x05 (family ID), DL = 0x25 (model ID, revision), P54LM, 2.9 V, step level Ax: DH = 0x05 (family ID), DL = 0x25 (model ID, revision). CPUID: family = 0x5, model = 0x2. Model 2, revision 5: FDIV bug fixed. 60, 66 MHz: 80501. 50/75, 60/90, 66/100, 60/120, 66/133 MHz: 80502. 2.41.3 Intel Pentium P55C CPU 50/150 MHz: 2.5 V, November 1994. 66/200 MHz (step level cC0): May 1996. Technology: 0.6 micron. 2.42 Intel Overdrive CPU for Intel Pentium CPU 2.42.1 Intel Pentium P54M CPU Overdrive for Intel Pentium P54C CPU. Technology: CMOS. ID: DH = 0x25 (model ID, family ID), DL = 0x2X (revision). 2.42.2 Intel Pentium P55CT CPU Overdrive for Intel Pentium P54C CPU. 120/133 MHz: for 60/66 MHz. 125 MHz: for 75 MHz. 150 MHz: for 90 MHz. 166 MHz: for 100 MHz. Technology: 0.35 micron CMOS. 2.43 AMD K5 CPU (K86 series) Intel Pentium CPU compatible. X86 to RISC Operation (ROP) translation. Superscalar: 5 stage, 3 integer pipelines, 1 FP pipeline. Cache: 16 kbyte instruction with predecode unit, 8 kbyte data (Harvard architecture), MESI compatible. Dynamic, block oriented, branch prediction with speculative execution. Announced: first quarter 1996. Package: 296 pin SPGA. Technology: 3.3 V, 0.5 micron, 3 layer CMOS (Fab 25, Texas), 0.35 micron CMOS (first quarter 1996). Announcements: AMD K6 CPU: vendor ID string: "AuthenticAMD", AMD K7 CPU. 2.43.1 AMD 5k86 K5 CPU (K86 series) Announced: end 1996. 2.43.2 AMD 5k86 SSA/5 CPU (K86 series) Pre-release AMD 5k86 K5 CPU: more internal wait states, incomplete BTB (Branch Target Buffer). Features: VME, I/O Breakpoints, TSC (Time Stamp Counter), Machine Check. May 1996. Step level: 0x50. 2.44 Cyrix 586 CPU Intel Pentium CPU compatible. Clock doubled/tripled. 16 kbyte unified cache: write-back, 4-way set-associative. Power management: SMM (System Management Mode), hardware suspend, stop-clock, FPU auto-idle. 50 MHz. 100 MHz (announced: third quarter 1995). 120 MHz. Not available anymore due to compatibility problems. 3.3 V, 5 V I/O. Superscalar: 7 stage, 2 isue. Branch prediction, branch target cache. Load/store unit. FPU: 4 64 bit write buffers. Package: 296 pin PGA. Technology: 0.5 micron CMOS (IBM, SGS-Thomson). Vendor ID string: "CyrixInstead". DIR0 register: 0x30. Cyrix M1 CPU. 2.45 NexGen Nx586/Nx587 CPU chipset Intel Pentium CPU instruction compatible. RISC (Reduced Instruction Set Computer): RISC86: interpreting (hardware) Intel Pentium CPU instruction set. Runs internally at 4 V; Compatibility with 5 V motherboard provided through the bus interface chip. 16 kbyte instruction cache, 16 kbyte data cache (Harvard architecture). External L2 cache controller for 256 kbyte or 1 Mbyte. NexGen Nx586 CPU: 60 MHz, 66 MHz. NexGen Nx587 NPX: 60 MHz, 66 MHz. March 1994. NexGen NxVL Vesa Local Bus interface: 60 MHz, 66 Mhz. NexGen NxPCI PCI Bus interface: October 1995. Superscalar: 2 integer units, FP adder (2 cycles), FP multiplier (2 cycles). Branch prediction. NexGen Nx586 CPU: 4 V, 9 W, 3.5E6 transistors, 0.5 micron CMOS. NexGen Nx587 NPX: 4 V, 1.1 W, 0.7E6 transistors, 0.5 micron CMOS. NexGen NxVL Vesa Local Bus interface: 5 V, 1.0 W, 0.5 micron CMOS. 75 MHz: September 1994. 80 MHz: September 1994. 90 MHz: September 1994. 100 MHz. 133 MHz: December 1994. Manufactured by IBM. 2.46 Intel Pentium Pro P6 CPU Upward compatible with all previous iapx CPUs (RISC core with X86 translation). Superscalar: 12 stage, 3 isue, instruction pool, fetch/decode unit, dispatch/execution unit (2 AGU (Address Generation Unit): 1 load, 1 store, 1 JEU (Jump Execution Unit), 2 IEU (Integer Execution Unit), 1 FEU (Floating Execution Unit)), retire unit. ECC. Fault Analysis & Recovery. Functional Redundancy Checking. Multiple branch prediction, data flow analysis, speculative execution. Level 1 cache: 8 kbyte instruction, 8 kbyte data (Harvard architecture). 256 kbyte level 2 cache: MESI support. 120 MHz. 133 MHz: 2.9 V, 14 W. 150 MHz: November 1995. 166 MHz. 180 MHz. 200 MHz: November 1995, 0.35 micron technology. Technology: 0.6 micron biCMOS, precharged domino logic. 5.5E6 transistors. ID: DH = 0x06 (model ID, family ID), DL = 0xXX (revision). 2.46.1 Intel Pentium Pro P6L CPU Intel Pentium Pro P6 CPU without level 2 cache. 2.46.2 Intel announcements P7, Merced (VLIW): 14E6 transistors, Santa Clara, CA: 1998. 2.47 Intel Overdrive P6 CPU 2.47.1 Intel Overdrive P6T CPU ID: DH = 0x16 (model ID, family ID), DL = 0xXX (revision). 2.48 IBM 6x86 CPU IBM 6x86-P120+ CPU. IBM 6x86-P133+ CPU. IBM 6x86-P150+ CPU. IBM 6x86-P166+ CPU. March 1996. 2.49 Cyrix 6x86 CPU Superpipelined scalar: 2 integer units, FPU (Floating Point Unit). Features: register renaming, out-of-order execution, data dependancy removal, branch prediction, speculative execution. 256 entry 4-way set-associative BTB (Branch Target Buffer). 16 kbyte unified cache: 4-way set-associative, write-back. 256 byte instruction cache: fully-associative. Multiprocessing support: SLiC/MP, OpenPIC interrupt architecture. 64 bit data bus. 3.3 V, 5 V tolerant I/O. 100 MHz (Cyrix 6x86-P120+GP CPU). 110 MHz (Cyrix 6x86-P133+GP CPU). 120 MHz (Cyrix 6x86-P150+GP CPU). 133 MHz (Cyrix 6x86-P166+GP CPU). October 1995. Package: 296 pin PGA (Pin Grid Array) (P54C socket compatible). Richardson, Texas. Cyrix M1 CPU. 2.50 NexGen Nx686 CPU Cache: 16 kbyte instruction, 32 kbyte data (Harvard architecture). Level 2 cache controller. 180 MHz. Technology: IBM 0.35 micron 5 layer metal CMOS. 6E6 transistors. 2.51 RISC CPU (Reduced Instruction Set Computer) Recently IBM announced to increase their effort on the development of the IBM, Motorola PowerPC CPU. They expect Microsoft's Windows NT (New Technology) running on a RISC (Reduced Instruction Set Computer) processor (theirs) to be the Microsoft MS-DOS / IBM PC/AT / Intel X86 CPU follow-up. In this section the non Intel X86 CPUs for which Microsoft's Windows NT is available are described (DEC DECchip-2106[468] CPU, MIPS R4X00 CPU, IBM, Motorola PowerPC CPU). For completeness some other RISC CPUs are described too (Sun Sparc CPU, HP PA CPU). PISC CPU (Parallel Instruction Set Computer): integrated DSP's (Digital Signal Processor). 2.51.1 DEC DECchip-210 CPU RISC (Reduced Instruction Set Computer). 64 bit architecture. 64/128 bit data bus. Super scalar: 2 64 bit integer units, floating point unit. 21064-AA: 150 MHz: 3.3 V, end 1992, 200 MHz: external speed: 25, 50, 100 MHz, 3.3 V, end 1992, 35 W. 21064-AA: 2 level cache, 250 MHz: 3.3 V, June 1994, 300 MHz: 3.3 V, June 1994. 21064: 166 MHz: November 1994, 233 MHz: November 1994. 21066: 21064 with PCI controller, DRAM/VRAM controller, graphics interface, 166 MHz, 7W, 200 MHz. 21068: low cost 21066, 66 MHz, December 1993, 20 W, 100 MHz, December 1993. Alpha. Used in DEC Alpha AXP. 2.51.2 MIPS R4000 CPU RISC (Reduced Instruction Set Computer). 64 bit data bus. 64 bit address bus. data and address bus are multiplexed. 8 kbyte instruction cache, 8 kbyte data cache (Harvard architecture): both direct mapped. MIPS R4000MC/R4000SC CPU: secondary external cache controller (128 bit bus). 100 MHz: 5V. LSI Logic LR4000PC CPU: 50 MHz, 0.7 micron CMOS. LSI Logic LR4000MC CPU. LSI Logic LR4000SC CPU: internal / external clock rate selectable 1/2, 1/3, 1/4, 100 MHz maximum. Also available from NEC, IDT and Toshiba. 2.51.3 MIPS R4200 CPU 16 kbyte instruction cache, 8 kbyte data cache (Harvard architecture): both direct mapped. 80 MHz: 3.3 V (also available from NEC). 2.51.4 MIPS R4400 CPU 16 kbyte instruction cache, 16 kbyte data cache (Harvard architecture): both direct mapped. MIPS R4400MC/R4400SC CPU: secondary external cache controller (128 bit bus). 100 MHz: 5 V. 100 MHz: 3.3 V. 133 MHz: 5 V. 133 MHz: 3.3 V. 150 MHz: 5 V. 150 MHz: 3.3 V. 200 MHz: 3.3 V, May 1994. Also available from NEC, IDT and Toshiba. 2.51.5 MIPS Orion R4600 CPU Designed by QED. 16 kbyte instruction cache, 16 kbyte data cache (Harvard architecture): both 2-way set associative. 100 MHz: 5 V (also available from IDT). 100 MHz: 3.3 V (also available from Toshiba). 133 MHz: April 1994. 150 MHz. 2.51.6 IBM, Motorola PowerPC CPU RISC (Reduced Instruction Set Computer). 64 bit architecture. Somerset Alliance: IBM, Motorola, Apple; Austin, Texas; February 1991. Somerset Design Center: Austin; 601, 603, 604, 620. Motorola, Israel; IBM, North Carolina: microcontrollers. PowerOpen Association: Apple, IBM, Motorola, Groupe Bull, Harris, Tadpole Technology, Thomson-CSF, Lobby group: Ford will use a PowerPC microcontroller in over 6,000,000 cars; Canon will use the PowerPC; Parsytec will use the PowerPC in its parallel computers. 401: (embedded microprocessor), 3.3 V, third quarter 1994. 20 MHz, 25 MHz, 33 MHz. 601: (personal computers). 64 bit external data bus. 32 bit address bus. 32 kbyte cache. 50 MHz: 3.6 V, fourth quarter 1994, 60 MHz, 66 MHz: 3.6 V, 9 W, fourth quarter 1994, 80 MHz: 3.6 V, 85 SPECint92, 105 SPECfp92, 8 W, fourth quarter 1994, used in Apple Power Macintosh and IBM RS/6000 100 MHz: November 1994, 4 W, IBM 0.5 micron CMOS, 135 MHz (announced: fourth quarter 1994). POWER (Performance Optimization With Enhanced RISC). MC98601. 602: (advanced consumer electronics, handheld computers). 66 MHz: February 1995. 603: low power (notebooks). 8 kbyte cache. 50 MHz: October 1993, 66 MHz: 3.3 V, October 1994, 80 MHz: October 1994, 75 SPECint92, 85 SPECfp92. Troubles running SoftPC; probably a 603+ will be developed by Apple. 603e: 16 kbyte cache. 100 MHz: October 1995, 1.2 W, 120 MHz: October 1995. 604: (high performance desktop computers, workstations). 75 MHz: 3.3 V, December 1994, 100 MHz: 3.3 V, December 1994, 120 MHz: 3.3 V, SPECint92 180, SPECfp92 180, 133 MHz: 3.3 V, SPECint92 200. package: ceramic QFP (Quad Flat Package), ceramic ball grid array. 3.3 V, die size: 13 x 15 mm, 3.6E6 transistors, technology: 0.5 micron CMOS. 615: 80X86 interpreter (hardware) (announced: fourth quarter 1994). Intel ODP CPU pin compatible. 620: (servers). 64 bit data bus. 64 bit address bus. Units: 2 integer, 2 floating point, 2 branch, jump. 32 kbyte instruction cache. POWER2 (Performance Optimization With Enhanced RISC 2). 71.5 MHz: 126 SPECint92, 260 SPECfp92, 130 MHz: 3.3 V, 133 MHz: October 1994, 150 MHz: 3.3 V. 630: (announced). 64 bit data bus. 64 bit address bus. multi-chip CPU: core, cache, controller. POWER3 (Performance Optimization With Enhanced RISC 3). 2.51.7 Sun Sparc CPU RISC (Reduced Instruction Set Computer). Texas Instruments SuperSPARC CPU (Viking). Texas Instruments SuperSPARC II CPU (announced). Texas Instruments UltraSPARC CPU (announced). Fujitsu MicroSPARC II CPU. Ross/Fujitsu Hypersparc CPU. 2.51.8 HP PA CPU (Precision Architecture) RISC (Reduced Instruction Set Computer). HP invested over $1,000,000,000 in this CPU and agreed with Intel to co-operate in the development of a new 64 bit RISC CPU using this architecture. 2.52 Motorola CPU In this section the Motorola CPU series, used in the Apple Macintosh personal computers and the Commodore Amiga home computers are described. Bit numbering: small endian. Byte numbering: big endian. 2.52.1 Motorola MC6800 CPU 8 bit data bus. 16 bit address bus. 1 MHz. 2 MHz. August 1974. 2.52.2 Motorola MC6802 CPU Motorola MC6800 CPU with extra features: 256 byte scratch pad at location 0, internal clock oscillator. Hitachi 6802W CPU: Motorola MC6802 CPU. 2.52.3 Motorola MC68HC11 CPU Motorola MC6802 CPU with extra features: some 16 bit instructions, on-board peripherals. 2.52.4 Motorola MC6809 CPU Optimized for high level languages. Motorola MC6809E CPU: external clock input for external sync. 2.52.5 Motorola MC68000 CPU 16 bit data bus. 24 bit address bus. September 1979. Used in Atari ST, Commodore Amiga, Apple Lisa, Macintosh. 2.52.6 Motorola MC68008 CPU 8 bit data bus. 20 bit address bus. Motorola MC68000 CPU instruction compatible. Same core as Motorola MC68000 CPU. 1985. 2.52.7 Motorola MC68302 CPU Integrated Multi-Protocol CPU. Motorola MC68000/MC68008 CPU core. System Integration Block: independent DMA, on-chip 1152 byte DPRAM, 3 timers including watchdog, on-chip clock generator with output, low power stand-by modes, 4 programmmable chip selects, programmable address mapping, parallel I/O ports with interrupt capability, interrupt controller, bus arbitration logic. Communications proccessor: RISC processor (Reduced Instruction Set Computer), 3 independent full duplex SCCs, supporting HDLC/SDLC, UART, BISYNC, DDCMP, V.110 rate adaption, transfer mode protocols, supporting user configureable protocols using microcode, 6 serial DMA channels, Flexible Physical Interface, using IDL, GCI, PCM, NMSI, SCP for synchronous communications, 2 serial management controllers to support GCI and IDL. 16.667 MHz. 2.52.8 Motorola MC68010 CPU Motorola MC68000 CPU upward instruction compatible: more instructions, more instructions with restart capabilities after interrupts. Motorola MC68000 CPU pin compatible. 1984. 2.52.9 Motorola MC68340 microprocessor Embedded version of Motorola MC68010 CPU. Included features: 2 DMA channels, 2 serial I/O channels, 2 multiple mode 16 bit timers, 4 programmable chip select signals, system failure protection. 16.78 MHz: 5 V. Package: 144 pin CQFP (Ceramic Quad Flat Package), 145 pin PGA (Pin Grid Array). 2.52.10 Motorola MC68020 CPU Motorola MC6800 CPU / Motorola MC68010 CPU upward instruction compatible. Extra features: extra instructions (32 bit multiplication and division), extra addressing modes. Modes: user mode, supervisor mode. 32 bit data bus. 32 bit address bus. 256 byte instruction cache. MMU (Memory Management Unit): Motorola MC68851 Paged MMU. NPX: Motorola MC68881 NPX, Motorola MC68882 NPX. 16.67 MHz. 20 MHz. 25 MHz. 33.33 MHz. Motorola MC68020RC CPU. Motorola MC68020RL CPU. Motorola MC68020RP CPU. Motorola MC68020FC CPU. Motorola MC68020FE CPU. 1982. Used in Amiga, Apple Macintosh, Sun3. 2.52.11 Motorola MC68030 CPU MMU (Memory Management Unit), 16 kbyte burst mode. 256 byte instruction cache, 256 byte data cache (Harvard architecture). 25 MHz. Motorola MC68030RC CPU. Motorola MC68030RL CPU. Motorola MC68030RP CPU. Motorola MC69030FE CPU. NPX: Motorola MC68881 NPX or faster Motorola MC68882 NPX. 1987. Used in Amiga 3000, Sun3, NeXT. 2.52.12 Motorola MC68040 CPU MMU (Memory Management Unit), FPU (Floating Point Unit), pipelined, clock doubled. 4 kbyte instruction cache, 4 kbyte data cache (Harvard Architecture). 25 MHz: January 1991. 33 MHz: January 1991. 40 MHz. 1.2E6 transistors. Used in Amiga 4000, Apple Macintosh, NeXT. 2.52.13 Motorola MC68LC040 CPU Motorola MC68040 CPU without FPU (Floating Point Unit). 2.52.14 Motorola MC68040V CPU Low power version (3.3 V) of the Motorola MC68040 CPU, no FPU (Floating Point Unit). Used in DraCo, Apple Powerbook. 2.52.15 Motorola MC68050 CPU Never released. 2.52.16 Motorola MC68060 CPU 32 bit data bus. 32 bit address bus. Enhanced FPU (Floating Point Unit). Power management. 8 kbyte instruction cache, 8 kbyte data cache (Harvard architecture). Cache line bursts. 3.3 V. Superscalar. Branch Target Buffer (BTB). Branch prediction and elimination. 50 MHz: April 1994. 66 MHz: April 1994. Used in DraCo, Amiga accelerator boards. Compiled, Copyright 1993, 1994, 1995, 1996, by A. Offerman. Permission to use, copy, or distribute this document in a non-commercial way for non-commercial use is hereby granted, provided that this copyright and permission notice appear in all copies. All other rights reserved. This document is provided "as is" without expressed or implied warranty. The specific products and their respective manufacturers are not to be taken as endorsements of, nor commercials for, the manufacturer.