;================================================================== ABS Absolute Value Operation: |D|->D (parallel move) Assembler Syntax: ABS D (parallel move) Instruction Format: ABS D D = (A,B) ;================================================================== ADC Add Long with Carry Operation: S+C+D -> D (parallel move) Assembler Syntax: ADC S,D (parallel move) Instruction Format: ADC S,D S = (X,Y) D = (A,B) ;================================================================== ADD Add Operation: S+D -> D (parallel move) Assembler Syntax: ADD S,D (parallel move) Instruction Format: ADD S,D S = (A,B,X,Y,X0,Y0,X1,Y1) D = (A,B) ;================================================================== ADDL Shift Left and Add Accumulators Operation: S+2*D -> D (parallel move) Assembler Syntax: ADDL S,D (parallel move) Instruction Format: ADDL S,D S = (A,B) D = (A,B) ;================================================================== ADDR Shift Right and Add Accumulators Operation: S + D / 2 -> D (parallel move) Assembler Syntax: ADDR S,D (parallel move) Instruction Format: ADDR S,D S = (A,B) D = (A,B) ;================================================================== AND Logical AND Operation: S & D[47:24] -> D[47:24] (parallel move) where & denotes the logical AND operator Assembler Syntax: AND S,D (parallel move) Instruction Format: AND S,D S = (X0,X1,Y0,Y1) D = (A,B) ;================================================================== ANDI AND Immediate with Control Register Operation: #xx & D -> D where & denotes the logical AND operator Assembler Syntax: AND(I) #xx,D Instruction Format: ANDI #xx,D #xx = 8-bit Immediate Short Data D = (MR,CCR,OMR) ;================================================================== ASL Aritmetic Shift Accumulator Left Operation: 55 47 23 0 +--+------+------+ C<-|<-|<-----|<-----|<--0 (parallel move) +--+------+------+ Assembler Syntax: ASL D (parallel move) Instruction Format: ASL D D = (A,B) ;================================================================== ASR Arithmetic Shift Accumulator Right Operation: 55 47 23 0 +--+------+------+ +->|->|----->|----->|--> C (parallel move) | +--+------+------+ +---+ Assembler Syntax: ASR D (parallel move) Instruction Format: ASR D D = (A,B) ;================================================================== BCHG Bit Test and Change Operation: D[n] -> C; D[n] -> D[n] Assembler Syntax: BCHG #n,X:ea BCHG #n,X:aa BCHG #n,X:pp BCHG #n,Y:ea BCHG #n,Y:aa BCHG #n,Y:pp BCHG #n,D Instruction Format: BCHG #n,X:ea BCHG #n,Y:ea BCHG #n,X:aa BCHG #n,Y:aa BCHG #n,X:pp BCHG #n,Y:pp BCHG #n,D #n = bit number ea = (Rn)-Nn (Rn)+Nn (Rn)- (Rn)+ (Rn) (Rn+Nn) -(Rn) Absolute address aa = 6-bit Absolute Short Address pp = 6-bit I/O Short Address D = ( X0,X1,Y0,Y1,A0,B0,A2,B2,A1,B1,A,B, Rn,Nn,Mn,SR,OMR,SP,SSH,SSL,LA,LC) ;================================================================== BCLR Bit Test and Clear Operation: D[n] -> C; 0 -> D[n] Assembler Syntax: BCLR #n,X:ea BCLR #n,X:aa BCLR #n,X:pp BCLR #n,Y:ea BCLR #n,Y:aa BCLR #n,Y:pp BCLR #n,D Instruction Format: BCLR #n,X:ea BCLR #n,Y:ea BCLR #n,X:aa BCLR #n,Y:aa BCLR #n,X:pp BCLR #n,Y:pp BCLR #n,D #n = bit number ea = (Rn)-Nn (Rn)+Nn (Rn)- (Rn)+ (Rn) (Rn+Nn) -(Rn) Absolute address aa = 6-bit Absolute Short Address pp = 6-bit I/O Short Address D = ( X0,X1,Y0,Y1,A0,B0,A2,B2,A1,B1,A,B, Rn,Nn,Mn,SR,OMR,SP,SSH,SSL,LA,LC) ;================================================================== BSET Bit Test and Set Operation: D[n] -> C; 1 -> D[n] Assembler Syntax: BSET #n,X:ea BSET #n,X:aa BSET #n,X:pp BSET #n,Y:ea BSET #n,Y:aa BSET #n,Y:pp BSET #n,D Instruction Format: BSET #n,X:ea BSET #n,Y:ea BSET #n,X:aa BSET #n,Y:aa BSET #n,X:pp BSET #n,Y:pp BSET #n,D #n = bit number ea = (Rn)-Nn (Rn)+Nn (Rn)- (Rn)+ (Rn) (Rn+Nn) -(Rn) Absolute address aa = 6-bit Absolute Short Address pp = 6-bit I/O Short Address D = ( X0,X1,Y0,Y1,A0,B0,A2,B2,A1,B1,A,B, Rn,Nn,Mn,SR,OMR,SP,SSH,SSL,LA,LC) ;================================================================== BTST Bit Test Operation: D[n] -> C Assembler Syntax: BTST #n,X:ea BTST #n,X:aa BTST #n,X:pp BTST #n,Y:ea BTST #n,Y:aa BTST #n,Y:pp BTST #n,D Instruction Format: BTST #n,X:ea BTST #n,Y:ea BTST #n,X:aa BTST #n,Y:aa BTST #n,X:pp BTST #n,Y:pp BTST #n,D #n = bit number ea = (Rn)-Nn (Rn)+Nn (Rn)- (Rn)+ (Rn) (Rn+Nn) -(Rn) Absolute address aa = 6-bit Absolute Short Address pp = 6-bit I/O Short Address D = ( X0,X1,Y0,Y1,A0,B0,A2,B2,A1,B1,A,B, Rn,Nn,Mn,SR,OMR,SP,SSH,SSL,LA,LC) ;================================================================== CLR Clear Accumulator Operation: 0 -> D (parallel move) Assembler Syntax: CLR D (parallel move) Instruction Format: CLR D D = (A,B) ;================================================================== CMP Compare Operation: S2 - S1 (parallel move) Assembler Syntax: CMP S1,S2 (parallel move) Instruction Format: CMP S1,S2 S1 = (A,B,X0,Y0,X1,Y1) S2 = (A,B) ;================================================================== CMPM Compare Magnitude Operation: |S2| - |S1| (parallel move) Assembler Syntax: CMPM S1,S2 (parallel move) Instruction Format: CMPM S1,S2 S1 = (A,B,X0,Y0,X1,Y1) S2 = (A,B) ;================================================================== DIV Divide Iteration Operation: If D[55] ^ S[23] = 1 55 47 23 0 +----+------------+------------+ then |<---|<-----------|<-----------| <- C + S -> D +----+------------+------------+ Destination Accumulator D 55 47 23 0 +----+------------+------------+ else |<---|<-----------|<-----------| <- C - S -> D +----+------------+------------+ Destination Accumulator D where ^ denotes the logical exclusive OR operator Assembler Syntax: DIV S,D Instruction Format: DIV S,D S = (X0,Y0,X1,Y1) D = (A,B) ;================================================================== DO Start Hardware Loop Operation: Assembler Syntax: SP+1->SP;LA->SSH;LC->SSL;X:ea->LC DO X:ea,expr SP+1->SP;PC->SSH;SR->SSL;expr-1->LA 1->LF SP+1->SP;LA->SSH;LC->SSL;X:aa->LC DO X:aa,expr SP+1->SP;PC->SSH;SR->SSL;expr-1->LA 1->LF SP+1->SP;LA->SSH;LC->SSL;Y:ea->LC DO Y:ea,expr SP+1->SP;PC->SSH;SR->SSL;expr-1->LA 1->LF SP+1->SP;LA->SSH;LC->SSL;Y:aa->LC DO Y:aa,expr SP+1->SP;PC->SSH;SR->SSL;expr-1->LA 1->LF SP+1->SP;LA->SSH;LC->SSL;#xxx->LC DO #xxx,expr SP+1->SP;PC->SSH;SR->SSL;expr-1->LA 1->LF SP+1->SP;LA->SSH;LC->SSL;S->LC DO S,expr SP+1->SP;PC->SSH;SR->SSL;expr-1->LA 1->LF End of Loop: SSL(LF)->SR;SP-1->SP SSH->LA;SSL->LC;SP-1->SP Restrictions: The "end-of-loop" comparison previously described actually occurs at instruction fetch time. That is, LA is being compared with PC when the instruction at LA-2 is being executed. Therefore, instructions which acceses the program controller register and/or change program flow canot be used in locations LA-2, LA-1, or LA. Proper DO loop operation is not guaranteed if an instruction starting at address LA-2, LA-1, or LA specifies one of the program controller registers SR, SP, SSL, LA, LC, or (implicitly) PC as a destination register. Similary, the SSH program controller register may not be specified as a source or destination register in an instruction starting at address LA-2,LA-1, or LA. Additionally, the SSH register cannot be specified as a source register in the DO instruction itself and LA cannot be used as a target for jumps to subroutine (i.e., JSR JScc, JSSET, or JSCLR to LA). A DO instruction cannot be repeated using the REP instruction. The following instructions cannot begin at the indicated position(s) near the end of a DO loop: At LA-2, LA-1, and LA DO MOVEC from SSH MOVEM from SSH MOVEP from SSH MOVEC to LA, LC, SR, SP, SSH, or SSL MOVEM to LA, LC, SR, SP, SSH, or SSL MOVEP to LA, LC, SR, SP, SSH, or SSL ANDI MR ORI MR Two word instructions which read LC, SP, or SSL At LA-1 Single-word instructions (except REP) which read LC, SP, or SSL, JCLR, JSET, two-word JMP, two word Jcc. At LA any two-word instruction Jcc REP JCLR RESET JSET RTI JMP RTS JScc STOP JSR WAIT Other Restrictions: DO SSH,xxxx JSR to (LA) whenever the loop flag (LF) is set JScc to (LA) whenever the loop flag (LF) is set JSCLR to (LA) whenever the loop flag (LF) is set JSSET to (LA) whenever the loop flag (LF) is set A DO instruction cannot be repeated using the REP instruction. Instruction Format: DO X:ea,expr DO Y:ea,expr DO X:aa,expr DO Y:aa,expr DO #xxx,expr DO S,expr expr = 16-bit Absolute Adress ea = (Rn)-Nn (Rn)+Nn (Rn)- (Rn)+ (Rn) (Rn+Nn) -(Rn) aa = 6-bit Absolute Short Address #xxx = 12-bit Immediate Short Data S = (X0,X1,Y0,Y1,A0,B0,A2,B2,A1,B1,A,B SR,OMR,SP,SSL,LA,LC,Rn,Nn,Mn) NOTE 1: Implementation Notes: For DO SP,expr The actual value that will be load into the loop counter (LC) is the value of the stack pointer (SP) before the execution of the DO instruction, incremented by 1. Thus, if SP=3, the execution of the DO SP,expr instruction will load the loop counter (LC) with the value LC = 4. For DO SSL,expr The LC will be loaded with the previous value wich was saved on the stack by the DO instruction itself. NOTE 2: If A or B is specified as a source operand, the accumulator value is optionally shifted according to the scaling mode bits in the status register. If the data out of the shifter indicates that the accumulator extension is in use, the 24-bit data is limited to a maximum positive or negative saturation constant. The shifted and limited value is loaded into LC, although A or B remain unchanged. ;================================================================== ENDDO End Current DO Loop Operation: SSL(LF)->SR;SP-1->SP SSH->LA;SSL->LC;SP-1->SP Assembler Syntax: ENDDO Restrictions: Due to pipelining and the fact that the ENDDO instruction accesses the program controller registers, the ENDDO instruction must not be immediately preceded by any of the following instructions: Immediately before ENDDO MOVEC to LA, LC, SR, SSH, SSL, or SP MOVEM to LA, LC, SR, SSH, SSL, or SP MOVEP to LA, LC, SR, SSH, SSL, or SP MOVEC from SSH MOVEM from SSH MOVEP from SSH ORI MR ANDI MR Also, the ENDDO instruction cannot be the next to last(LA-1) or last (LA) instruction in a DO loop. Instruction Format: ENDDO ;================================================================== EOR Logical Exclusif OR Operation: S ^ D[47:24]->D[47:24] (parallel move) where ^ denotes the logical exclusive OR operator Assembler Syntax: EOR S,D (parallel move) Instruction Format: EOR S,D S = (X0,X1,Y0,Y1) D = (A,B) ;================================================================== ILLEGAL Illegal Instruction Interrupt Operation: Begin Illegal Instruction exception processing Assembler Syntax: ILLEGAL Instruction Format: ILLEGAL ;================================================================== Jcc Jump Conditionally JCC JCS JEC JEQ JES JGE JGT JLC JLE JLS JLT JMI JNE JNR JPL JNN Operation: Assembler Syntax: If cc, then 0xxx -> PC Jcc xxx else PC+1 -> PC If cc, then ea -> PC Jcc ea else PC+1 -> PC Restrictions: A Jcc instruction used within a DO loop cannot begin at the address LA within that DO loop. A Jcc instruction cannot be repeated using the REP instruction. Instruction Format: Jcc xxx Jcc ea xxx = 12-bit Short Jump Adress ea = (Rn)-Nn (Rn)+Nn (Rn)- (Rn)+ (Rn) (Rn+Nn) -(Rn) Absolute address ;================================================================== JCLR Jump if Bit Clear Operation: If S[n] = 0, then xxxx -> PC else PC+1 -> PC Assembler Syntax: JCLR #n,X:ea,xxxx JCLR #n,X:aa,xxxx JCLR #n,X:pp,xxxx JCLR #n,Y:ea,xxxx JCLR #n,Y:aa,xxxx JCLR #n,Y:pp,xxxx JCLR #n,S,xxxx Restrictions: A JCLR instruction cannot be repeated using the REP instruction. A JCLR located at LA, LA-1, or LA-2 of the DO loop cannot specify the program controller registers SR, SP, SSH, SSL, LA, or LC as its target. JCLR SSH or JCLR SSL cannot follow an instruction that changes the SP. Instruction Format: JCLR #n,X:ea,xxxx JCLR #n,Y:ea,xxxx JCLR #n,X:aa,xxxx JCLR #n,Y:aa,xxxx JCLR #n,X:pp,xxxx JCLR #n,Y:pp,xxxx JCLR #n,S,xxxx #n = bit number ea = (Rn)-Nn (Rn)+Nn (Rn)- (Rn)+ (Rn) (Rn+Nn) -(Rn) aa = 6-bit Absolute Short Address pp = 6-bit I/O Short Address S = ( X0,X1,Y0,Y1,A0,B0,A2,B2,A1,B1,A,B, Rn,Nn,Mn,SR,OMR,SP,SSH,SSL,LA,LC) ;================================================================== JMP Jump Operation: Assembler Syntax: 0xxx -> PC JMP xxx ea -> PC JMP ea Instruction Format: JMP xxx JMP ea xxx = 12-bit Short Jump Address ea = (Rn)-Nn (Rn)+Nn (Rn)- (Rn)+ (Rn) (Rn+Nn) -(Rn) Absolute address ;================================================================== JScc Jump to Subroutine Conditionally JSCC JSCS JSEC JSEQ JSES JSGE JSGT JSLC JSLE JSLS JSLT JSMI JSNE JSNR JSPL JSNN Operation: Assembler Syntax: If cc, then SP+1->SP;PC->SSH;SR->SSL;0xxx->PC JScc xxx else PC+1->PC If cc, then SP+1->SP;PC->SSH;SR->SSL;ea->PC JScc ea else PC+1->PC Restrictions: A JScc instruction used within a DO loop cannot specify the loop address (LA) as its target. A JScc instruction used within in a DO loop cannot begin at the address LA within that DO loop. A JScc instruction cannot be repeated using the REP instruction. Instruction Format: JScc xxx JScc ea xxx = 12-bit Short Jump Address ea = (Rn)-Nn (Rn)+Nn (Rn)- (Rn)+ (Rn) (Rn+Nn) -(Rn) Absolute address ;================================================================== JSCLR Jump to Subroutine if Bit Clear Operation: If S[n]=0, then SP+1->SP;PC->SSH;SR->SSL;xxxx->PC else PC+1->PC Assembler Syntax: JSCLR #n,X:ea,xxxx JSCLR #n,X:aa,xxxx JSCLR #n,X:pp,xxxx JSCLR #n,Y:ea,xxxx JSCLR #n,Y:aa,xxxx JSCLR #n,Y:pp,xxxx JSCLR #n,S,xxxx Restrictions: A JSCLR instruction used within a DO lopp cannot specify the loop address (LA) as its target. A JSCLR located at LA, LA-1, or LA-2 of a DO loop, cannot specify the program controller registers SR, SP, SSH, SSL, LA, or LC as its target. JSCLR SSH or JSCLR SSL cannot follow an instruction that changes the SP. A JSCLR instrcuction cannot be repeated using the REP instruction. Instruction Format: JSCLR #n,X:ea,xxxx JSCLR #n,X:aa,xxxx JSCLR #n,X:pp,xxxx JSCLR #n,Y:ea,xxxx JSCLR #n,Y:aa,xxxx JSCLR #n,Y:pp,xxxx JSCLR #n,S,xxxx xxxx = 16-bit Absolute Address #n = bit number ea = (Rn)-Nn (Rn)+Nn (Rn)- (Rn)+ (Rn) (Rn+Nn) -(Rn) aa = 6-bit Absolute Short Address pp = 6-bit I/O Short Address S = (X0,X1,Y0,Y1,A0,B0,A2,B2,A1,B1,A,B, Rn,Nn,Mn,SR,OMR,SP,SSH,SSL,LA,LC) ;================================================================== JSET Jump if Bit Set Operation: If S[n] = 1, then xxxx->PC else PC+1->PC Assembler Syntax: JSET #n,X:ea,xxxx JSET #n,X:aa,xxxx JSET #n,X:pp,xxxx JSET #n,Y:ea,xxxx JSET #n,Y:aa,xxxx JSET #n,Y:pp,xxxx JSET #n,S,xxxx Restrictions: A JSET instruction used within a DO loop cannot specify the loop address (LA) as its target. A JSET located at LA, LA-1, or LA-2 of a DO loop cannot specify the program controller registers SR, SP, SSH, SSL, LA, or LC as its target. JSET SSH or JSET SSL cannot follow an instruction that changes the SP. A JSET instruction cannot be repeated using the REP instruction. Instruction Format: JSET #n,X:ea,xxxx JSET #n,X:aa,xxxx JSET #n,X:pp,xxxx JSET #n,Y:ea,xxxx JSET #n,Y:aa,xxxx JSET #n,Y:pp,xxxx JSET #n,S,xxxx xxxx = 16-bit Absolute Address #n = bit number ea = (Rn)-Nn (Rn)+Nn (Rn)- (Rn)+ (Rn) (Rn+Nn) -(Rn) aa = 6-bit Absolute Short Address pp = 6-bit I/O Short Address S = (X0,X1,Y0,Y1,A0,B0,A2,B2,A1,B1,A,B, Rn,Nn,Mn,SR,OMR,SP,SSH,SSL,LA,LC) ;================================================================== JSR Jump to Subroutine Operation: Assembler Syntax: SP+1->SP;PC->SSH;SR->SSL;0xxx->PC JSR xxx SP+1->SP;PC->SSH;SR->SSL;ea->PC JSR ea Restrictions: A JSR instruction used within a DO loop cannot specify the loop address (LA) as its target. A JSR instruction used within a DO loop cannot begin at the address LA within that DO loop. A JSR instruction cannot be repeated using the REP instruction. Instruction Format: JSR xxx JSR ea xxx = 12-bit Short Jump Address ea = (Rn)-Nn (Rn)+Nn (Rn)- (Rn)+ (Rn) (Rn+Nn) -(Rn) Absolute address ;================================================================== JSSET Jump to Subroutine if Bit Set Operation: If S[n] = 1, then SP+1->SP;PC->SSH;SR->SSL;xxxx->PC else PC+1->PC Assembler Syntax: JSSET #n,X:ea,xxxx JSSET #n,X:aa,xxxx JSSET #n,X:pp,xxxx JSSET #n,Y:ea,xxxx JSSET #n,Y:aa,xxxx JSSET #n,Y:pp,xxxx JSSET #n,S,xxxx Restrictions: A JSSET instruction used within a DO loop cannot specify the loop address (LA) as its target. A JSSET located at LA, LA-1, or LA-2 ofa DO loop, cannot specify the program controller registers SR, SP, SSH, SSL, LA, or LC as its target. JSSET SSH or JSSET SSL cannot follow an instruction that changes the SP. A JSSET instruction cannot be repeated using the REP instruction. Instruction Format: JSSET #n,X:ea,xxxx JSSET #n,X:aa,xxxx JSSET #n,X:pp,xxxx JSSET #n,Y:ea,xxxx JSSET #n,Y:aa,xxxx JSSET #n,Y:pp,xxxx JSSET #n,S,xxxx xxxx = 16-bit Absolute Address #n = bit number ea = (Rn)-Nn (Rn)+Nn (Rn)- (Rn)+ (Rn) (Rn+Nn) -(Rn) aa = 6-bit Absolute Short Address pp = 6-bit I/O Short Address S = ( X0,X1,Y0,Y1,A0,B0,A2,B2,A1,B1,A,B, Rn,Nn,Mn,SR,OMR,SP,SSH,SSL,LA,LC) ;================================================================== LSL Logical Shift Left Operation: 47 24 +------------+ C <-|<-----------|<- 0 (parallel move) +------------+ Assembler Syntax: LSL D (parallel move) Instruction Format: LSL D D = (A,B) ;================================================================== LSR Logical Shift Right Operation: 47 24 +------------+ 0 ->|----------->|-> C (parallel move) +------------+ Assembler Syntax: LSR D (parallel move) Instruction Format: LSR D D = (A,B) ;================================================================== LUA Load Update Address Operation: ea -> D Assembler Syntax: LUA ea,D Instruction Format: LUA ea,D ea = (Rn)-Nn (Rn)+Nn (Rn)- (Rn)+ D = (Rn,Nn) ;================================================================== MAC Signed Multiply-Accumulate Operation: D+-S1*S2 -> D (parallel move) Assembler Syntax: MAC (+-)S1,S2,D (parallel move) Instruction Format: MAC (+-)S1,S2,D S1 = (X0,Y0,X1,Y1) S2 = (X0,Y0,X1,Y1) D = (A,B) ;================================================================== MACR Signed Multiply-Accumulate and Round Operation: D+-S1*S2+r -> D (parallel move) Assembler Syntax: MACR (+-)S1,S2,D (parallel move) Instruction Format: MACR (+-)S1,S2,D S1 = (X0,Y0,X1,Y1) S2 = (X0,Y0,X1,Y1) D = (A,B) ;================================================================== MOVE Move Data Operation: S->D Assembler Syntax: MOVE S,D Instruction Format: MOVE ;================================================================== I Immediate Short Data Move Operation: (.....),#xx->D Assembler Syntax: (.....) #xx,D Instruction Format: (.....) #xx,D #xx = 8-bit Immediate Short Data D = (X0,X1,Y0,Y1,A0,B0,A2,B2,A1,B1,A,B,Rn,Nn) ;================================================================== R Register to Register Data Move Operation: (.....);S->D Assembler Syntax: (.....) S,D Instruction Format: (.....) S,D S = (X0,X1,Y0,Y1,A0,B0,A2,B2,A1,B1,A,B,Rn,Nn) D = (X0,X1,Y0,Y1,A0,B0,A2,B2,A1,B1,A,B,Rn,Nn) ;================================================================== U Address Register Update Operation: (.....); ea->Rn Assembler Syntax: (.....) ea Instruction Format: (.....) ea ea = (Rn)-Nn (Rn)+Nn (Rn)- (Rn)+ ;================================================================== X: X Memory Data Move Operation: Assembler Syntax: (.....); X:ea->D (.....) X:ea,D (.....); X:aa->D (.....) X:aa,D (.....); S->X:ea (.....) S,X:ea (.....); S->X:aa (.....) S,X:aa (.....); #xxxxxx->D (.....) #xxxxxx,D Instruction Format: (.....) X:ea,D (.....) S,X:ea (.....) #xxxxxx,D (.....) X:aa,D (.....) S,X:aa #xxxxxx = 24-bit Immediate Data aa = 6-bit Absolute Short Address ea = (Rn)-Nn (Rn)+Nn (Rn)- (Rn)+ (Rn+Nn) -(Rn) Absolute address S = (X0,X1,Y0,Y1,A0,B0,A2,B2,A1,B1,A,B,Rn,Nn) D = (X0,X1,Y0,Y1,A0,B0,A2,B2,A1,B1,A,B,Rn,Nn) ;================================================================== X:R X Memory and Register Data Move Operation: Assembler Syntax: Class I Class I (...); X:ea->D1;S2->D2 (...) X:ea,D1 S2,D2 (...); S1->X:ea;S2->D2 (...) S1,X:ea S2,D2 (...); #xxxxxx->D1;S2->D2 (...) #xxxxxx,D1 S2,D2 Class II Class II (...); A->X:ea;X0->A (...) A,X:ea X0,A (...); B->X:ea;X0->B (...) B,X:ea X0,B Instruction Format: Class I (.....) X:ea,D1 S2,D2 (.....) S1,X:ea S2,D2 (.....) #xxxxxx,D1 S2,D2 ea = (Rn)-Nn (Rn)+Nn (Rn)- (Rn)+ (Rn) (Rn+Nn) -(Rn) Absolute address Immediate data S1 = (X0,X1,A,B) D1 = (X0,X1,A,B) S2 = (A,B) D2 = (Y0,Y1) Class II (.....) A,X:ea X0,A (.....) B,X:ea X0,B ea = (Rn)-Nn (Rn)+Nn (Rn)- (Rn)+ (Rn) (Rn+Nn) -(Rn) Absolute address ;================================================================== Y: Y Memory Data Move Operation: Assembler Syntax: (.....); Y:ea->D (.....) Y:ea,D (.....); Y:aa->D (.....) Y:aa,D (.....); S->Y:ea (.....) S,Y:ea (.....); S->Y:aa (.....) S,Y:aa (.....); #xxxxxx->D (.....) #xxxxxx,D Instruction Format: (.....) Y:ea,D (.....) S,Y:ea (.....) #xxxxxx,D (.....) Y:aa,D (.....) S,Y:aa #xxxxxx = 24-bit Immediate Data aa = 6-bit Absolute Short Address ea = (Rn)-Nn (Rn)+Nn (Rn)- (Rn)+ (Rn+Nn) -(Rn) Absolute address S = (X0,X1,Y0,Y1,A0,B0,A2,B2,A1,B1,A,B,Rn,Nn) D = (X0,X1,Y0,Y1,A0,B0,A2,B2,A1,B1,A,B,Rn,Nn) ;================================================================== R:Y Register and Y Memory Data Move Operation: Assembler Syntax: Class I Class I (...); S1->D1;Y:ea->D2 (...) S1,D1 Y:ea,D2 (...); S1->D1;S2->Y:ea (...) S1,D1 S2,Y:ea (...); S1->D1;#xxxxxx->D2 (...) S1,D1 #xxxxxx,D2 Class II Class II (...); Y0->A;A->Y:ea (...) Y0,A A,Y:ea (...); Y0->B;B->Y:ea (...) Y0,B B,Y:ea Instruction Format: Class I (...) S1,D1 Y:ea,D2 (...) S1,D1 S2,Y:ea (...) S1,D1 #xxxxxx,D2 ea = (Rn)-Nn (Rn)+Nn (Rn)- (Rn)+ (Rn) (Rn+Nn) -(Rn) Absolute address Immediate data S1 = (A,B) D1 = (X0,X1) S2 = (Y0,Y1,A,B) D2 = (Y0,Y1,A,B) Class II (...) Y0,A A,Y:ea (...) Y0,B B,Y:ea ea = (Rn)-Nn (Rn)+Nn (Rn)- (Rn)+ (Rn) (Rn+Nn) -(Rn) Absolute address ;================================================================== L: Long Memory Data Move Operation: Assembler Syntax: (...); X:ea->D1;Y:ea->D2 (...) L:ea,D (...); X:aa->D1;Y:aa->D2 (...) L:aa,D (...); S1->X:ea;S2->Y:ea (...) S,L:ea (...); S1->X:aa;S2->Y:aa (...) S,L:aa Instruction Format: (...) L:ea,D (...) S,L:ea (...) L:aa,D (...) S,L:aa aa = 6-bit Absolute Short Address ea = (Rn)-Nn (Rn)+Nn (Rn)- (Rn)+ (Rn) (Rn+Nn) -(Rn) Absolute address S = (A10,B10,X,Y,A,B,AB,BA) D = (A10,B10,X,Y,A,B,AB,BA) ;================================================================== X:Y X Y Memory Data Move Operation: Assembler Syntax: (...);X:->D1;Y:->D2 (...) X:,D1 Y:,D2 (...);X:->D1;S2->Y: (...) X:,D1 S2,Y: (...);S1->X:;Y:->D2 (...) S1,X: Y:,D2 (...);S1->X:;S2->Y: (...) S1,X: S2,Y: Instruction Format: (...) X:,D1 Y:,D2 (...) X:,D1 S2,Y: (...) S1,X: Y:,D2 (...) S1,X: S2,Y: eax = (Rn)+Nn (Rn)- (Rn)+ (Rn) eay = (Rn)+Nn (Rn)- (Rn)+ (Rn) S1 = (X0,X1,A,B) D1 = (X0,X1,A,B) S2 = (Y0,Y1,A,B) D2 = (Y0,Y1,A,B) ;================================================================== MOVEC Move Control Register Operation: Assembler Syntax: X:ea->D1 MOVEC X:ea,D1 X:aa->D1 MOVEC X:aa,D1 S1->X:ea MOVEC S1,X:ea S1->X:aa MOVEC S1,X:aa Y:ea->D1 MOVEC Y:ea,D1 Y:aa->D1 MOVEC Y:aa,D1 S1->Y:ea MOVEC S1,Y:ea S1->Y:aa MOVEC S1,Y:aa S1->D2 MOVEC S1,D2 S2->D1 MOVEC S2,D1 #xxxx->D1 MOVEC #xxxx,D1 #xx->D1 MOVEC #xx,D1 Restrictions: NOTE: The following restrictions represent very unusual operations, which probably would never be used but are listed only for completeness. A MOVEC instruction used within a DO loop which specifies SSH as the source operand or LA, LC, SR, SP, SSH, or SSL as the destination operand cannot begin at the address LA-2, LA-1, or LA within that DO loop. A MOVEC instruction which specifies SSH as the source operand or LA, LC, SSH, SSL, or SP as the destination operand cannot be used immediately before a DO instruction. A MOVEC instruction which specifies SSH as the source operand or LA, LC, SR, SSH, SSL, or SP as the destination operand cannot be used immediately before an ENDDO instruction. A MOVEC instruction which specifies SSH as the source operand or SR, SSH, SSL, or SP as the destination operand cannot be used immediately before an RTI instruction. A MOVEC instruction which specifies SSH as the source operand or SSH, SSL, or SP as the destination operand cannot be used immediately before an RTS instruction. A MOVEC instruction which specifies SP as the destination operand cannot be used immediately before a MOVEC, MOVEM, or MOVEP instruction which specifies SSH or SSL as the source operand. A MOVEC SSH,SSH instruction is illegal and cannot be used. Instruction Format: MOVEC X:ea,D1 MOVEC X:aa,D1 MOVEC S1,X:ea MOVEC S1,X:aa MOVEC Y:ea,D1 MOVEC Y:aa,D1 MOVEC S1,Y:ea MOVEC S1,Y:aa MOVEC S1,D2 MOVEC S2,D1 MOVEC #xxxx,D1 MOVEC #xx,D1 #xxxx = Immediate Data #xx = 8-bit Immediate Short Data aa = 6-bit Absolute Short Address ea = (Rn)-Nn (Rn)+Nn (Rn)- (Rn)+ (Rn) (Rn+Nn) -(Rn) Absolute address S1 = (Mn,SR,OMR,SP,SSH,SSL,LA,LC) D1 = (Mn,SR,OMR,SP,SSH,SSL,LA,LC) S2 = (X0,X1,Y0,Y1,A0,B0,A2,B2,A1,B1,A,B,Rn,Nn,Mn,SR, OMR,SP,SSH,SSL,LA,LC) D2 = (X0,X1,Y0,Y1,A0,B0,A2,B2,A1,B1,A,B,Rn,Nn,Mn,SR, OMR,SP,SSH,SSL,LA,LC) ;================================================================== MOVEM Move Program Memory Operation: Assembler Syntax: S->P:ea MOVEM S,P:ea S->P:aa MOVEM S,P:aa P:ea->D MOVEM P:ea,D P:aa->D MOVEM P:aa,D Restrictions: A MOVEM instruction used within a DO loop which specifies SSH as the source operand or LA, LC, SR, SP, SSH, or SSL as the destination operand cannot begin at the address LA-2, LA-1, or LA within that DO loop. A MOVEM instruction which specifies SSH as the source operand or LA, LC, SSH, SSL, or SP as the destination operand cannot be used immediately before a DO instruction. A MOVEM instruction which specifies SSH as the source operand or LA, LC, SR, SSH, SSL, or SP as the destination operand cannot be used immediately before an ENDDO instruction. A MOVEM instruction which specifies SSH as the source operand or SR, SSH, SSL, or SP as the destination operand cannot be used immediately before an RTI instruction. A MOVEM instruction which specifies SSH as the source operand or SSH, SSL, or SP as the destination operand cannot be used immediately before an RTS instruction. A MOVEM instruction which specifies SP as the destination operand cannot be used immediately before a MOVEC, MOVEM, or MOVEP instruction which specifies SSH or SSL as the source operand. Instruction Format: MOVEM S,P:ea MOVEM S,P:aa MOVEM P:ea,D MOVEM P:aa,D aa = 6-bit Absolute Short Data ea = (Rn)-Nn (Rn)+Nn (Rn)- (Rn)+ (Rn) (Rn+Nn) -(Rn) Absolute address S = (X0,X1,Y0,Y1,A0,B0,A2,B2,A1,B1,A,B,Rn,Nn,Mn,SR,OMR,SP,SSH, SSL,LA,LC) D = (X0,X1,Y0,Y1,A0,B0,A2,B2,A1,B1,A,B,Rn,Nn,Mn,SR,OMR,SP,SSH, SSL,LA,LC) ;================================================================== MOVEP Move Peripheral Data Operation: Assembler Syntax: X:pp->D MOVEP X:pp,D X:pp->X:ea MOVEP X:pp,X:ea X:pp->Y:ea MOVEP X:pp,Y:ea X:pp->P:ea MOVEP X:pp,P:ea S->X:pp MOVEP S,X:pp #xxxxxx->X:pp MOVEP #xxxxxx,X:pp X:ea->X:pp MOVEP X:ea,X:pp Y:ea->X:pp MOVEP Y:ea,X:pp P:ea->X:pp MOVEP P:ea,X:pp Y:pp->D MOVEP Y:pp,D Y:pp->X:ea MOVEP Y:pp,X:ea Y:pp->Y:ea MOVEP Y:pp,Y:ea Y:pp->P:ea MOVEP Y:pp,P:ea S->Y:pp MOVEP S,Y:pp #xxxxxx->Y:pp MOVEP #xxxxxx,Y:pp X:ea->Y:pp MOVEP X:ea,Y:pp Y:ea->Y:pp MOVEP Y:ea,Y:pp P:ea->Y:pp MOVEP P:ea,Y:pp Restrictions: NOTE: The following restrictions represent very unusual operations, which probably would never be used but are listed only for completeness. A MOVEP instruction used within a DO loop which specifies SSH as the source operand or LA, LC, SR, SP, SSH, or SSL as the destination operand cannot begin at the address LA-2, LA-1, or LA within that DO loop. A MOVEP instruction which specifies SSH as the source operand or LA, LC, SSH, SSL, or SP as the destination operand cannot be used immediately before a DO instruction. A MOVEP instruction which specifies SSH as the source operand or LA, LC, SR, SSH, SSL, or SP as the destination operand cannot be used immediately before an ENDDO instruction. A MOVEP instruction which specifies SSH as the source operand or SR, SSH, SSL, or SP as the destination operand cannot be used immediately before an RTI instruction. A MOVEP instruction which specifies SSH as the source operand or SSH, SSL, or SP as the destination operand cannot be used immediately before an RTS instruction. A MOVEP instruction which specifies SP as the destination operand cannot be used immediately before a MOVEC, MOVEM, or MOVEP instruction which specifies SSH or SSL as the source operand. Instruction Format: MOVEP X:pp,D MOVEP X:pp,X:ea MOVEP X:pp,Y:ea MOVEP X:pp,P:ea MOVEP S,X:pp MOVEP #xxxxxx,X:pp MOVEP X:ea,X:pp MOVEP Y:ea,X:pp MOVEP P:ea,X:pp MOVEP Y:pp,D MOVEP Y:pp,X:ea MOVEP Y:pp,Y:ea MOVEP Y:pp,P:ea MOVEP S,Y:pp MOVEP #xxxxxx,Y:pp MOVEP X:ea,Y:pp MOVEP Y:ea,Y:pp MOVEP P:ea,Y:pp #xxxxxx = Immediate Data pp = 6-bit I/O Short Address ea = (Rn)-Nn (Rn)+Nn (Rn)- (Rn)+ (Rn) (Rn+Nn) -(Rn) Absolute address S = (X0,X1,Y0,Y1,A0,B0,A2,B2,A1,B1,A,B,Rn,Nn,Mn,SR,OMR,SP,SSH, SSL,LA,LC) D = (X0,X1,Y0,Y1,A0,B0,A2,B2,A1,B1,A,B,Rn,Nn,Mn,SR,OMR,SP,SSH, SSL,LA,LC) ;================================================================== MPY Signed Multiply Operation: +-S1*S2->D (parallel move) Assembler Syntax: MPY (+-)S1,S2,D (parallel move) Instruction Format: MPY (+-)S1,S2,D S1 = (X0,Y0,X1,Y1) S2 = (X0,Y0,X1,Y1) D = (A,B) ;================================================================== MPYR Signed Multiply and Round Operation: +-S1*S2+r->D (parallel move) Assembler Syntax: MPYR (+-)S1,S2,D (parallel move) Instruction Format: MPYR (+-)S1,S2,D S1 = (X0,Y0,X1,Y1) S2 = (X0,Y0,X1,Y1) D = (A,B) ;================================================================== NEG Negate Accumulator Operation 0-D->D (parallel move) Assembler Syntax: NEG D (parallel move) Instruction Format: NEG D D = (A,B) ;================================================================== NOP No operation Operation PC = PC +1 Assembler Syntax: NOP Instruction Format: NOP ;================================================================== NORM Normalize Accumulator Iteration Operation: If ~E & U & ~Z = 1, then ASL D and Rn-1 -> Rn else if E = 1, then ASR D and Rn+1 -> Rn else NOP where ~ denotes the logical complement & denotes the logical AND operator Assembler Syntax: NORM Rn,D Instruction Format: NORM Rn,D ;================================================================== NOT Logical Complement Operation: ~D[47:24] -> D[47:24] (parallel move) where ~ denotes the logical NOT operator Assembler Syntax: NOT D (parallel move) Instruction Format: NOT D D = (A,B) ;================================================================== OR Logical Inclusive OR Operation: S + D[47:24] -> D[47:24] (parallel move) where + denotes the logical inclusive OR operator Assembler Syntax: OR S,D (parallel move) Restrictions: The ORI #xx,MR instruction cannot be used immediately before an ENDDO or RTI instruction and cannot be one of the last three instructions in a DO loop (at LA-2, LA-1, or LA). Instruction Format: OR S,D S = (X0,X0,X1,Y1) D = (A,B) ;================================================================== ORI OR Immediate with Control Register Operation: #xx + D -> D where + denotes the logical inclusive OR operator Assembler Syntax: OR(I) #xx,D Instruction Format: ORI #xx,D D = (MR,CCR,OMR) ;================================================================== REP Repeat Next Instruction Operation: LC -> TEMP; X: -> LC or LC -> TEMP; X: -> LC or LC -> TEMP; Y: -> LC or LC -> TEMP; Y: -> LC or LC -> TEMP; S -> LC or LC -> TEMP; #xxx -> LC Repeat next instruction until LC=1 TEMP -> LC Assembler Syntax: REP X: REP X: REP Y: REP Y: REP S REP #xxx Restrictions: The REP instruction can repeat any single-word instruction except the REP instruction itself and any instruction that changes program flow. The following instructions are not allowed to follow an REP instruction: Instruction Format: REP X: REP X: REP Y: REP Y: REP S REP #xxx ea = (Rn)-Nn (Rn)+Nn (Rn)- (Rn)+ (Rn) (Rn+Nn) -(Rn) aa = 6-bit Absolute Short Address #xxx = 12-bit Immediate Short Data S = (X0,Y0,X1,Y1,A2,A1,A0,B2,B1,B0,A,B,R0-R7 N0-N7,M0-M7,SR,OMR,SP,SSH,SSL,LA,LC) ;================================================================== RESET Reset On-Chip Peripheral Devices Operation: Reset the interrupt priority register and all on-chip peripherals Assembler Syntax: RESET Restrictions: A RESET instruction cannot be the last instruction in a DO loop (at LA). Instruction Format: RESET ;================================================================== RND Round Accumulator Operation: D+r -> D (parallel move) Assembler Syntax: RND D (parallel move) Instruction Format: RND D D = (A,B) ;================================================================== ROL Rotate Left Operation: 47 24 +------------+ <-C-|<-----------|<-+ (parallel move) | +------------+ | +-------------------+ Assembler Syntax: ROL D (parallel move) Instruction Format: ROL D D = (A,B) ;================================================================== ROR Rotate Right Operation: 47 24 +------------+ +C->|----------->|->-+ (parallel move) | +------------+ | +--------------------+ Assembler Syntax: ROR D (parallel move) Instruction Format: ROR D D = (A,B) ;================================================================== RTI Return from Interrupt Operation: SSH -> PC SSL -> SR SP - 1 -> SP Assembler Syntax: RTI Restrictions: Due to pipelining in the program controller and the fact that the RTI instruction accesses certain controller registers, the RTI instruction must be immediately preceded by any of the following instructions: Immediately before RTI: MOVEC to LA, LC, SSH, SSL, or SP MOVEM to LA, LC, SSH, SSL, or SP MOVEP to LA, LC, SSH, SSL, or SP MOVEC from SSH MOVEM from SSH MOVEP from SSH ANDI MR or ANDI CCR ORI MR or ORI CCR An RTI instruction cannot be the LAST instruction in a DO loop (at LA). An RTI instruction cannot be repeated using the REP instruction. Instruction Format: RTI ;================================================================== RTS Return from Subroutine Operation: SSH -> PC; SP - 1 -> SP Assembler Syntax: RTS Restrictions: Due to pipelining in the program controller and the fact that the RTS instruction accesses certain controller registers, the RTS instruction must be immediately preceded by any of the following instructions: Immediately before RTS: MOVEC to LA, LC, SSH, SSL, or SP MOVEM to LA, LC, SSH, SSL, or SP MOVEP to LA, LC, SSH, SSL, or SP MOVEC from SSH MOVEM from SSH MOVEP from SSH An RTS instruction cannot be the LAST instruction in a DO loop (at LA). An RTS instruction cannot be repeated using the REP instruction. Instruction Format: RTS ;================================================================== SBC Subtract Long with Carry Operation: D - S - C -> D (parallel move) Assembler Syntax: SBC S,D (parallel move) Instruction Format: SBC S,D S = (X,Y) D = (A,B) ;================================================================== STOP Stop Instruction Processing Operation: Enter the STOP processing state and stop the clock oscillator Assembler Syntax: STOP Restrictions: A STOP instruction cannot be used in a fast interrupt routine. A STOP instruction cannot be the last instruction in a DO loop (at LA). A STOP instruction cannot be repeated using REP instruction. Instruction Format: STOP ;================================================================== SUB Subtract Operation: D - S -> D (parallel move) Assembler Syntax: SUB S,D (parallel move) Instruction Format: SUB S,D S = (A,B,X,Y,X0,Y0,X1,Y1) D = (A,B) ;================================================================== SUBL Shift Left and Subtract Accumulators Operation: 2*D - S -> D (parallel move) Assembler Syntax: SUBL S,D (parallel move) Instruction Format: SUBL S,D S = (A,B) D = (A,B) ;================================================================== SUBR Shift Right and Subtract Accumulators Operation: D / 2 - S -> D (parallel move) Assembler Syntax: SUBR S,D (parallel move) Instruction Format: SUBR S,D S = (A,B) D = (A,B) ;================================================================== SWI Software Interrupt Operation: Begin SWI exception processing Assembler Syntax: SWI Restrictions: An SWI instruction cannot be used in a fast interrupt routine. An SWI instruction cannot be repeated using REP instruction. Instruction Format: SWI ;================================================================== Tcc Transfer Conditionally TCC TCS TEC TEQ TES TGE TGT TLC TLE TLS TLT TMI TNE TNR TPL TNN Operation: If cc, then S1 -> D1 If cc, then S1 -> D1 and S2 -> D2 Assembler Syntax: Tcc S1,D1 Tcc S1,D1 S2,D2 Instruction Format: Tcc S1,D1 Tcc S1,D1 S2,D2 S1 = (A,B,X0,Y0,X1,Y1) D1 = (A,B) S2 = (Rn) D2 = (Rn) ;================================================================== TFR Transfer Data ALU Register Operation: S -> D (parallel move) Assembler Syntax: TFR S,D (parallel move) Instruction Format: TFR S,D S = (A,B,X0,Y0,X1,Y1) D = (A,B) ;================================================================== TST Test Accumulator Operation: S - 0 (parallel move) Assembler Syntax: TST S (parallel move) Instruction Format: TST S S = (A,B) ;================================================================== WAIT Wait for Interrupt Operation: Disable clocks to the processor core and enter the WAIT processing state. Assembler Syntax: WAIT Restrictions: A WAIT instruction cannot be used in a fast interrupt routine. A WAIT instruction cannot be the last instruction in a DO loop (at LA). A WAIT instruction cannot be repeated using REP instruction. Instruction Format: WAIT