From ???@0x00000E8B Tue Nov 17 16:22:22 1998 Path: news.nic.utwente.nl!surfnet.nl!news-ge.switch.ch!isdnet!newsfeed.cwix.com!206.191.82.230!attc1!attcanada!wn4feed!worldnet.att.net!207.24.196.41!nntphub.cb.lucent.com!ssbunews.ih.lucent.com!not-for-mail From: bohdan@ihgp4.ih.lucent.com (-Bodnar,B.L.) Newsgroups: comp.arch Subject: Re: Why Positive Clock Edges? Date: 17 Nov 1998 14:02:18 GMT Organization: Lucent Technologies Lines: 62 Message-ID: <72rvla$oum@ssbunews.ih.lucent.com> References: NNTP-Posting-Host: ihgp4.ih.lucent.com Xref: news.nic.utwente.nl comp.arch:49332 Status: N In article , Mark Thorson wrote: >Why did the early TTL devices (e.g. 7490 and 7493) >use negative clock edges and the later ones (e.g. >74160 and 74193) use positive ones? > >I suppose the reason most control signals are >active low is that most of the time the signal >is not active, and in TTL the current is much >lower for a high signal than a low one. Or, it >could be that the noise immunity is higher for >a high than a low. > >In CMOS, does any reason other than tradition >favor one or the other? It seems like most chips >are clocked on rising edges and cleared or reset >with low-going pulses. I can't think of any >reason other than habit for maintaining this >practice. > This is an interesting question. I don't have an "authoritative answer", but I think I can provide some insight regarding this. A lot of computer gear from the 1960s and 1970s used active low logic (that is, "high" is a positive voltage "low" is something close to ground). The reason for this was because a 1 -> 0 transition took less time than a 0 -> 1 transition. This, in turn, was an artifact of the technology (no tristate logic drivers, for instance). I'll give you a concrete example: A typical I/O connection was a 133 ohms "minicomputer bus." This bus was driven by an open-collector driver and was terminated at the far end by an active terminator which usually consisted to two resistors in series and a reversed diode. The resistors formed a Thevenin equivalent resistance of 133 ohms and the diode was used to suppress reversed voltage pulses. When turned on, the collector-emitter resistance of the driver transistor was very low -- much lower than 133 ohms. If you draw the equivalent electrical circuit, you'll see that it takes MUCH LESS TIME to discharge the distributed capacitance in this transmission line than to charge it via the termination resistors (the resistors were typically selected to set the quiescent voltage on the bus to about 2.4 volts -- the equivalent of the minimum voltage for "1" in TTL technology.) Hence, active-low pulses were used to ensure maximum speed. Now, take a look at the totem-pole output circuit of a typical TTL gate: It consists of two NPN transistors in series. The bottom transistor has its emitter connected to ground and the collector going to the output pin of the chip. The output pin is connected to the top transistor's emitter via a diode (used to ensure that the phase splitter preceding the totem-pole output stage doesn't turn both transistors on at the same time). The collector of the top transistor is connected to Vcc via a resistor. It's clear that a 1->0 transition will take less time than a 0->1 transition. So, I think one of the reasons probably is an attempt to reduce propagation delay of a signal. With the driver architecture, a 1->0 transition will take less time than a 0->1 transition. Hence, negative pulse/edge clocking. Any other reasons? Cordially, Bohdan Bodnar bbodnar@lucent.com From ???@0x0000093D Wed Nov 18 21:24:33 1998 Path: news.nic.utwente.nl!surfnet.nl!news-ge.switch.ch!isdnet!howland.erols.net!news.sgi.com!enews.sgi.com!decwrl!pa.dec.com!nntpd.lkg.dec.com!oarsmn!dupcak From: dupcak@oarsmn.enet.dec.comX (Rob Dupcak) Newsgroups: comp.arch Subject: Re: Why Positive Clock Edges? Date: 17 Nov 1998 17:28:32 GMT Organization: Digital Equipment Corporation Lines: 36 Sender: dupcak@oarsmn (Rob Dupcak) Distribution: world Message-ID: <72sbo0$bk6$1@nntpd.lkg.dec.com> References: Reply-To: dupcak@oarsmn.enet.dec.comX NNTP-Posting-Host: oarsmn.enet.dec.com X-Newsreader: mxrn 6.18-32 Xref: news.nic.utwente.nl comp.arch:49336 Status: N In article , eee@netcom.com (Mark Thorson) writes: >In CMOS, does any reason other than tradition >favor one or the other? It seems like most chips >are clocked on rising edges and cleared or reset >with low-going pulses. I can't think of any >reason other than habit for maintaining this >practice. From a physical design perspective it is much easier/efficient to build NAND style logic than NOR style logic. (NORs which require larger PMOS devices which are inherently ~2-3 times as large as NMOS devices etc. etc. etc.) What does this have to do with anything... well clocked NAND type logic (whether it be a fully static or dynamic implementation) is in its active state when the clock is logically a '1' or switching to a '1'. (This puts a high voltage on the NMOS devices which then "turns on" the device.) Conversely, you could build the same circuits while swapping the NMOS and PMOS devices and arrive at logic which is active when the clock is logically '0' or switching to '0'. As mentionned earlier though, this would result in a physically larger circuit which is definitely an undesired trait. This is not to say it isn't done. One of the usual techniques to get around this, is to invert the clock and use the same circuits as before. Now I am glossing over some major circuit design issues but the general point is still valid - of course someone is going to jump all over this and point out that someone, somewhere did something different. Well, they are probably right... and I'll gladly let them design their PMOS zipper logic in their test chips. - Rob